The present invention relates to an electrically erasable programmable read-only memory (EEPROM) device, and more particularly to an EEPROM storing data of a multilevel.
The present application is based on Japanese Patent Application. No. 8-61352, Japanese Patent Application. No. 8-61443, Japanese Patent Application. No. 8-61444 and Japanese Patent Application. No. 8-61449, the content of which is incorporated herein by reference.
As one of a means for increasing the capacity of an EEPROM, a multilevel storing EEPROM has been known capable of causing n (nxe2x89xa73)-level information to be stored in one memory cell. A four-level data storing structure is arranged such that each cell is provided with one of four threshold voltages and the threshold voltages correspond to 2-bit information expressed as xe2x80x9c0, 0xe2x80x9d, xe2x80x9c0, 1xe2x80x9d, xe2x80x9c1, 0xe2x80x9d and xe2x80x9c1, 1xe2x80x9d.
To read data in the memory cell in which n-level information has been stored, data read from the cell must be compared with (nxe2x88x921) reference voltages. Accordingly, (nxe2x88x921) sense amplifiers have been required (refer to, for example, Japanese Patent KOKAI Publication No. 61-117796). A four-level data storing EEPROM must have three sense amplifiers.
Therefore, the four-level data storing EEPROM involves the storing density in the memory cell being doubled as compared with the EEPROM having binary data storing cells. Although the area of the memory cells can be halved, the area of the sense amplifiers is tripled. Thus, a required high density structure cannot be formed. In particular, an EEPROM having a sense amplifier provided for each bit line for the purpose of page reading cannot easily be formed into a large capacity structure because the number of the sense amplifiers is enlarged excessively.
A read-only memory has been disclosed in Japanese Patent KOKAI Publication No. 62-54896 which is capable of decreasing the number of sense amplifiers by using an output from a sense amplifier, which has determined cell data, to control the reference voltages of other sense amplifiers. However, the foregoing structure cannot be applied to a writable memory.
On the other hand, a multilevel data storing EEPROM for causing n (nxe2x89xa73) types of threshold voltages to be stored in the memory cells must distribute the threshold voltages in each of narrow ranges when data to be stored is written. Therefore, writing is performed little by little and whether or not data has been written in each memory cell within a required threshold voltage range is verified between writing operations. If a cell, in which data has not sufficiently been written, exists, additional writing of the cell has been performed. The foregoing technology is arranged to cause optimum writing to be performed for each memory cell and is known as xe2x80x9cbit-by-bit verificationxe2x80x9d. The concept of the bit-by-bit verification has been disclosed in Japanese Patent KOKAI Publication No. 3-295098.
The technology disclosed in Japanese Patent KOKAI Publication No. 3-295098 relates to a binary-data storing EEPROM. The bit-by-bit verification applicable to a multilevel data storing EEPROM has been disclosed in Japanese Patent KOKAI Publication No. 7-93979. However, the apparatus disclosed in Japanese Patent KOKAI Publication No. 7-93979 requires (nxe2x88x921) sense amplifiers and (nxe2x88x921) verify circuits. Although the memory cell is able to store larger quantity of data and thus a large quantity of data can be stored in a chip having the same area, the size of a circuit for controlling data read/write is enlarged excessively to form a highly integrated structure.
Moreover, the multilevel-data storing EEPROM involves the number of bits of signals for use therein, in particular, the signals for use in the input/output data line being different from the number of bits of signals for use in a circuit substrate for establishing the connection between the multilevel-data storing EEPROM with another integrated circuit apparatus, such as a processor. As a result, the multilevel-data storing EEPROM must have a circuit for converting the number of bits of the signal for use in the outside portion of the apparatus into the number of bits of the signal for use in the apparatus.
When the number of multilevel data is n (n is a natural number not smaller than 3) in the conventional multilevel-data storing EEPROM having the verify means, (nxe2x88x921) verify circuits must be provided. Therefore, also (nxe2x88x921) sense amplifiers and (nxe2x88x921) data latches must be provided to correspond to the verify circuits. As a result, the size of the circuit connected to the bit line, that is, the size of the column-system circuit, in particular, the number of the sense amplifiers and data latches cannot be reduced. Thus, a highly integrated structure cannot be realized.
Moreover, the circuit for converting the number of bits of the signal for use in the outside portion of the apparatus and the number of bits of the signal for use in the apparatus must be provided. Therefore, a highly integrated structure cannot be realized and a high speed input/output operation cannot be performed.
Accordingly, it is a first object of the present invention is to provide a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.
A second object of the present invention is to provide a nonvolatile semiconductor memory device capable of omitting a circuit for converting the number of bits and realizing both highly integrated structure and a high speed input/output operation.
The foregoing objects can be realized by the following nonvolatile semiconductor memory device.
According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing multilevel data are arranged in a matrix manner;
a bit line controller having latching means for latching data to be written in the memory cell when data is written in the memory cell and sensing/latching means for sensing and latching data read from the memory cell when data is read from the memory cell; and
a bit line for electrically connecting the bit line controller and the memory cell to each other, supplying data from the latching means to the memory cell when data is written in the memory cell and supplying read data from the memory cell to the sensing/latching means when data is read from the memory cell,
wherein when the number of multilevel data is n (n is a natural number not smaller than 4), the number of the latching means and the number of the sensing/latching means are m (m satisfies 2mxe2x88x921 less than nxe2x89xa62m (m is a natural number not smaller than 2).
According to the nonvolatile semiconductor memory device of the first aspect, when the number of multilevel data is n satisfying n=2m, m is the same as the number of bits of data input/output lines which are electrically connected to the bit line controller, and one bit data is assigned to each of the m latching means and the m sensing/latching means.
According to the nonvolatile semiconductor memory device of the first aspect, when data is read from the memory cell, the m sensing/latching means are sequentially operated from first sensing/latching means assigned to a first bit which is the most significant bit toward the m-th sensing/latching means assigned to the m-th bit which is the least significant bit.
According to the nonvolatile semiconductor memory device of the first aspect, the first sensing/latching means assigned to the first bit which is the most significant bit compares read data supplied from the memory cell through the bit line with a first reference voltage to output a result of a comparison representing whether or not read data is higher than the first reference voltage, and switches the level of a second reference voltage to be provided for a second sensing/latching means assigned to a second bit which is a next bit in accordance with the output result of the comparison.
According to the nonvolatile semiconductor memory device of the first aspect, the level of the m-th reference voltage to be provided for a sensing/latching means assigned to the m-th bit which is the least significant bit is switched 2mxe2x88x921 times in accordance with a result of a comparison between the (mxe2x88x921)-th reference voltage provided for the sensing/latching means assigned to the (mxe2x88x921)-th bit which is an upper bit and data read from the memory cell.
According to the nonvolatile semiconductor memory device of the first aspect, the number of bits of the data input/output line is the same as the number of bits of write data to be supplied to the apparatus from outside of the apparatus and the number of bits of read data to be output from the inside portion of the apparatus to the outside of the apparatus.
According to the nonvolatile semiconductor memory device of the first aspect, write data is supplied to the latching means from outside of the apparatus such that the number of bits of write data is not converted, and read data is output from the sensing/latching means to the outside of the apparatus such that the number of bits of read data is not converted.
According to the nonvolatile semiconductor memory device of the first aspect, 2m=n-level data, which appears on one bit line, is converted into m-bit and n-level data by the latching means and the sensing/latching means.
According to the nonvolatile semiconductor memory device of the first aspect, each of write data to be supplied from the latching means to the memory cell through the bit line and read data to be supplied from the memory cell to the sensing/latching means through the bit line is n multilevel data, and the bit line distinguishes each of n multilevel data in accordance with the level of voltage to supply data from the latching means to the memory cell and supply data from the memory cell to the sensing/latching means.
According to the nonvolatile semiconductor memory device of the first aspect, the memory cell for storing multilevel data includes a transistor having a variable threshold voltage, and the transistor having the variable threshold voltage distinguishes each of n multilevel data in accordance with the level of the threshold voltage and then store n multilevel data.
According to a second aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing multilevel data are arranged in a matrix manner;
a bit line controller having latching means for latching data to be written in the memory cell when data is written in the memory cell, sensing/latching means for sensing and latching data read from the memory cell when data is read from the memory cell and verify means for performing a verify operation to make a reference to data latched by the latching means and arranged to be written in the memory cell; and
a bit line for electrically connecting the bit line controller and the memory cell to each other, supplying data from the latching means into the memory cell when data is written in the memory cell and supplying read data from the memory cell to the sensing/latching means when data is read from the memory cell,
wherein when the number of multilevel data is n (n is a natural number not smaller than 4), the number of the latching means, the number of the sensing/latching means and the number of the verify means are m (m satisfies 2mxe2x88x921 less than nxe2x89xa62m (m is a natural number not smaller than 2).
According to the nonvolatile semiconductor memory device of the second aspect, when the number of multilevel data is n satisfying n=2m, m is the same as the number of bits of data input/output lines which are electrically connected to the bit line controller, and one bit data is assigned to each of the m latching means and the m sensing/latching means.
According to the nonvolatile semiconductor memory device of the second aspect, when data is read from the memory cell, the m sensing/latching means are sequentially operated from first sensing/latching means assigned to a first bit which is the most significant bit toward the m-th sensing/latching means assigned to the m-th bit which is the least significant bit, and when data is read from the memory cell for verification, the m sensing/latching means are sequentially operated from m-th sensing/latching means assigned to m-th bit which is the least significant bit toward the first sensing/latching means assigned to the first bit which is the most significant bit.
According to the nonvolatile semiconductor memory device of the second aspect, when data is read from the memory cell, the first sensing/latching means assigned to the first bit which is the most significant bit compares read data supplied from the memory cell through the bit line with a first reference voltage to output a result of a comparison representing whether or not read data is higher than the first reference voltage, and switches the level of a second reference voltage to be provided for a second sensing/latching means assigned to a second bit which is a next bit in accordance with the output result of the comparison, and when data is read from the memory cell for verification, the level of the second reference voltage to be provided for the second sensing/latching means assigned to the second bit which is the next bit is switched in accordance with read data latched by the first latching means assigned to the first bit which is the most significant bit.
According to the nonvolatile semiconductor memory device of the second aspect, when data is read from the memory cell, the level of the m-th reference voltage to be provided for a sensing/latching means assigned to the m-th bit which is the least significant bit is switched 2mxe2x88x921 times in accordance with a result of a comparison between the (mxe2x88x921)-th reference voltage provided for the sensing/latching means assigned to the (mxe2x88x921)-th bit which is an upper bit and data read from the memory cell.
According to the nonvolatile semiconductor memory device of the second aspect, when data is read from the memory cell, the sensing/latching means converts 2m=n-level data read to one bit line into n m-bit read data, when data is written in the memory cell, the latching means supplies m-bit n-level write data to data writing circuit for converting data into 2m=n-level write data for one bit line, and m-bit and n-level read data and m-bit and n-level write data are supplied as different data.
According to the nonvolatile semiconductor memory device of the second aspect, when data is read from the memory cell for verification, the latching means compares m-bit n-level write data with 2m=n-level data read to one bit line, activates the verify means when the write data and the read data coincide with each other and deactivates the verify means when the write data and the read data do not coincide with each other.
According to the nonvolatile semiconductor memory device of the second aspect, the number of bits of the data input/output lines is the same as each of the number of bits of write data to be supplied from outside of the apparatus into the apparatus and the number of bits of read data to be output from the inside portion of the apparatus to the outside of the apparatus.
According to the nonvolatile semiconductor memory device of the second aspect, write data is supplied from the outside of the apparatus to the latching means such that the number of bits of write data is not converted, and read data is output from the sensing/latching means to the outside of the apparatus such that the number of bits of read data is not converted.
According to the nonvolatile semiconductor memory device of the second aspect, each of write data to be supplied from the latching means to the memory cell through the bit line and read data to be supplied from the memory cell to the sensing/latching means through the bit line is n multilevel data, and the bit line distinguishes each of n multilevel data in accordance with the level of voltage to supply data from the latching means to the memory cell and supply data from the memory cell to the sensing/latching means.
According to the nonvolatile semiconductor memory device of the second aspect, each of write data to be supplied from the latching means to the memory cell through the bit line and read data to be supplied from the memory cell to the sensing/latching means through the bit line is n multilevel data, and the bit line distinguishes each of n multilevel data in accordance with the level of voltage to supply data from the latching means to the memory cell and supply data from the memory cell to the sensing/latching means.
According to the nonvolatile semiconductor memory device of the second aspect, the memory cell for storing multilevel data includes a transistor having a variable threshold voltage, and the transistor having the variable threshold voltage distinguishes each of n multilevel data in accordance with the level of the threshold voltage and then store n multilevel data.
According to a third aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing multilevel data are arranged in a matrix manner;
a bit line controller having latching function for latching data to be written in the memory cell when data is written in the memory cell and sensing/latching function for sensing and latching data read from the memory cell when data is read from the memory cell and in which when the number of multilevel data is n (n is a natural number not smaller than 4), the number of the latching function and the number of the sensing/latching function are m (m satisfies 2mxe2x88x921 less than nxe2x89xa62m (m is a natural number not smaller than 2);
a bit line for electrically connecting the bit line controller and the memory cell to each other, supplying data from the latching function into the memory cell when data is written in the memory cell and supplying read data from the memory cell to the sensing/latching function when data is read from the memory cell;
a writing circuit for selecting write control voltage corresponding to multilevel data in accordance with write data latched by the latching function when data is written in the memory cell and applying selected write control voltage to the bit line; and
a verify circuit for verifying data written in the memory cell,
wherein the verify circuit and the writing circuit is controlled in accordance with n write data latched by the latching function.
According to the nonvolatile semiconductor memory device of the third aspect, the latch function updates write data latched in the latch function to non-changed memory cell data when data has been written in the memory cell in a case where a result of verify read operation is valid.
According to the nonvolatile semiconductor memory device of the third aspect, data to be input to the latch function is controlled by the verify circuit and the writing circuit in accordance with latched write data in order to prevent change of updated write data during a verify read operation.
According to a fourth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell array formed of a plurality of memories each having a charge storage portion capable of storing n-level (nxe2x89xa73) data, a plurality of bit lines, a plurality of word lines, a plurality of program controllers and a plurality of data circuits, wherein the program controller selects a memory cell and applies write voltage to the selected memory cell, the data circuit is formed of m latches when m is a natural number satisfying 2mxe2x88x921 less than nxe2x89xa62m, holds first, second, . . . , n-th logical level write control data for controlling write control voltages to be applied to corresponding memory cells selected by the program control circuit, applies the write control voltages to the corresponding memory cells, selectively detects only a write state of the memory cell corresponding to the data circuit storing the write control data of a logical level except the first logical level, changes the logical level of the write control data in the data circuit corresponding to the memory cell which has brought to a predetermined write state to the first logical level, holds the logical level of write control data in the data circuit corresponding to the memory cell which has not reached the predetermined write state, and holds the logical level of write control data in the data circuit storing first logical level write control data in the first logical level, and write data is updated in accordance with the combination of states of m latches.
According to the nonvolatile semiconductor memory device of the fourth aspect, a verify circuit for updating write data generates write control voltage.
According to a fifth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing multilevel data are arranged in a matrix manner;
a bit line controller having data latch/sense amplifier for latching data to be written in the memory cell when data is written in the memory cell and sensing and latching data read from the memory cell when data is read from the memory cell such that when the number of multilevel data is 2m (m is a natural number not smaller than 2)=n-level, the number of the data latch/sense amplifier is m;
a bit line for connecting the data latch/sense amplifier and the memory cell to each other, supplying data from the data latch/sense amplifier into the memory cell when data is written in the memory cell and supplying read data from the memory cell to the data latch/sense amplifier when data is read from the memory cell;
a writing circuit for selecting write control voltage corresponding to multilevel data in accordance with write data latched by the data latch/sense amplifier when data is written in the memory cell and applying selected write control voltage to the bit line; and
a verify circuit for verifying whether or not written data has been brought to a required date storing state after data has been written in the memory cell.
According to a sixth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level (n is a natural number not smaller than 3) which can electrically be rewritten are arranged in a matrix manner;
threshold detection means for electrically charging the bit line connected to the memory cell through the memory cell and outputting multilevel data in the memory cell as a multilevel level potential to the bit line;
a sense amplifier for sensing the multilevel level bit line potential charged by the threshold detection means;
first, second, . . . , m-th data circuits for storing data to be written in the memory cell;
verify means for verifying whether or not the state after data has been written in the memory cell has been a required data storing state by using the threshold detection means; and
means for simultaneously updating contents of the data circuit formed of a data updating circuit for simultaneously updating the contents of the data circuit to again write data in only a memory cell in which data has not been sufficiently written in accordance with the contents of the data circuit and the state after data has been written in the memory cell,
wherein the data updating circuit makes a reference to the contents of one data circuit.
According to a seventh aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level (n is a natural number not smaller than 3) which can electrically be rewritten are arranged in a matrix manner;
threshold detection means for electrically charging the bit line connected to the memory cell through the memory cell and outputting multilevel data in the memory cell as a multilevel level potential to the bit line;
a sense amplifier for sensing the multilevel level potential of the bit line electrically charged by the threshold detection means by making a comparison with a reference voltage;
first, second, . . . , m-th data circuits for storing data to be written in the memory cell;
verify means for verifying whether or not the state after data has been written in the memory cell has been a required data storing state by using the threshold detection means; and
means for simultaneously updating contents of the data circuit, which is formed of a data updating circuit for simultaneously updating the contents of the data circuit to again write data in only a memory cell in which data has not been sufficiently written in accordance with the contents of the data circuit and the state after data has been written in the memory cell,
wherein the data updating circuit makes a reference to the contents of one data circuit, the means for simultaneously updating contents of the data circuit modifies the bit line to which the state after the memory cell writing operation has been performed is output and the reference voltage in accordance with the contents of the data circuit in order to cause the potential of the bit line to be sensed and stored as re-write data, holds the data storing state of the data circuit until the potential of the bit line is modified, operates the data circuit as a sense amplifier while storing the modified potential of the bit line and simultaneously updates the contents of the data circuit, and a writing operation and the simultaneous update of the contents of the data circuit in accordance with the contents of the data circuit are repeated until the memory cell is brought to a predetermined write state so that data is electrically written.
According to the nonvolatile semiconductor memory device of the fifth, sixth and seventh aspects, the memory cell is a NAND cell having a plurality of memory cell transistors, in series, connected, an end of the NAND cell is connected to the bit line through a first election gate, and another end of the NAND cell is connected to a source line through a second selection gate, the threshold detection means causes the voltage of the source line to be transferred to the bit line through the NAND cell, and voltages of non-selected control gates and voltages of the first and second selection gates are controlled in such a manner that voltage transfer performance of the non-selected memory cells and the first and second selection transistors is improved such that the voltage of the bit line is determined in accordance with the threshold voltage of the selected memory cell.
According to an eighth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level (n is a natural number not smaller than 4) which can electrically be rewritten are arranged in a matrix manner;
first, second, . . . , m-th (m is a natural number satisfying 2mxe2x88x921 less than nxe2x89xa62m) data circuits for storing data to be written in the memory cell; and
verify means for verifying whether or not the state after data has been written in the memory cell has been a required data storing state.
According to a ninth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level (n is a natural number not smaller than 3) which can electrically be rewritten are arranged in a matrix manner;
first, second, . . . , m-th (m is a natural number satisfying 2mxe2x88x921 less than nxe2x89xa62m) data circuits for storing data to be written in the memory cell;
verify means for verifying whether or not the state after data has been written in the memory cell has been a required data storing state; and
means for simultaneously pupdating contents of the data circuit, which is formed of a data updating circuit for simultaneously updating the contents of the data circuit to again write data in only a memory cell in which data has not been sufficiently written in accordance with the contents of the data circuit and the state after data has been written in the memory cell,
wherein the data update circuit makes a reference to the contents of one data circuit.
According to a tenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level (n is a natural number not smaller than 4) which can electrically be rewritten are arranged in a matrix manner;
threshold detection means for detecting the threshold voltage of the memory cell;
first, second, . . . , m-th (m is a natural number satisfying 2mxe2x88x921 less than nxe2x89xa62m ) data circuits for storing data to be written in the memory cell; and
verify means for verifying whether or not the state after data has been written in the memory cell has been a required data storing state,
wherein detection of the threshold voltage is performed such that first threshold detection voltage is applied to a gate electrode of the memory cell to determine whether the memory cell is (i) in a xe2x80x9c1xe2x80x9d state or (ii) in a xe2x80x9c2 or morexe2x80x9d state (i.e., xe2x80x9c2xe2x80x9d, xe2x80x9c3xe2x80x9d, . . . , or xe2x80x9cnxe2x80x9d state), second threshold detection voltage is applied to the gate electrode of the memory cell to determine whether the memory cell is (i) in the xe2x80x9c1 or 2xe2x80x9d state (i.e., xe2x80x9c1xe2x80x9d or xe2x80x9c2xe2x80x9d state) or (ii) in a xe2x80x9c3 or morexe2x80x9d state (i.e., xe2x80x9c3xe2x80x9d, xe2x80x9c4xe2x80x9d, . . . , or xe2x80x9cnxe2x80x9d state), and third to (nxe2x88x921)-th threshold detection voltage is applied to the gate electrode of the memory cell.
According to an eleventh aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level (n is a natural number not smaller than 3) which can electrically be rewritten are arranged in a matrix manner;
a data circuit for storing data to be written in the memory cell; and
verify means for verifying whether or not the state after data has been written in the memory cell has been a required data storing state,
wherein a writing operation is performed to realize n types of write states such that first writing of memory cells, in which writing of k types (k is a natural number satisfying 2 xe2x89xa6k  less than n) is performed, is substantially simultaneously performed, and writing of a memory cell in which (nxe2x88x92k) types of writing states are performed is performed before or after the first writing operation.
According to a twelfth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level (n is a natural number not smaller than 3) in which xe2x80x9c1xe2x80x9d state is an erase state, and xe2x80x9c2xe2x80x9d, xe2x80x9c3xe2x80x9d, . . . , of xe2x80x9cnxe2x80x9d state is a write state and which can electrically be rewritten are arranged in a matrix manner;
a data circuit for storing data to be written in the memory cell; and
verify means for verifying whether or not the state after data has been written in the memory cell has been a required data storing state,
wherein first writing of memory cells which are written in the xe2x80x9c3xe2x80x9d, . . . , or xe2x80x9cnxe2x80x9d state among the n types of writing operations is substantially simultaneously performed, and writing to xe2x80x9c2xe2x80x9d state is performed before or after the first writing operation.
According to the nonvolatile semiconductor memory device of the twelfth aspect, threshold voltages for writing xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c3xe2x80x9d, . . . , or xe2x80x9cnxe2x80x9d state satisfying the following relation;
xe2x80x9c1xe2x80x9d state less than xe2x80x9c2xe2x80x9d state less than xe2x80x9c3xe2x80x9d state less than  . . .  less than xe2x80x9cnxe2x80x9d state.
According to a thirteenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level and having storing states of xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c3xe2x80x9d, . . . , or xe2x80x9cnxe2x80x9d state (n is a natural number not smaller than 3) and being able to be electrically rewritten are arranged in a matrix manner;
a signal line for communicating data with the memory cell; and
a read data storing circuit for storing data read from the memory cell,
wherein an i-th reading operation is performed such that the threshold voltage of the memory cell is similar to xe2x80x9cixe2x80x9d state, higher than the xe2x80x9cixe2x80x9d state or lower than the xe2x80x9cixe2x80x9d state is determined, and read data is stored in the data storing circuit, and
when a j-th reading operation is performed in which the threshold voltage of the memory cell is similar to xe2x80x9cjxe2x80x9d state, higher than the xe2x80x9cjxe2x80x9d state or lower than the xe2x80x9cjxe2x80x9d state is determined, the potential of the signal line from which data in the memory cell has been output is changed by making a reference to data stored in the data storing circuit, and then the potential of the signal line is sensed.
According to a fourteenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level (n is a natural number not smaller than 3) which can electrically be rewritten are arranged in a matrix manner;
a signal line for communicating data with the memory cell;
a data circuit for storing data to be written in the memory cell; and
verify means for verifying whether or not the state after data has been written in the memory cell has been a required data storing state,
wherein reference to the potential of a signal line from which data to be written in the memory cell has been output is made two or more times to update the contents of the data circuit in such a manner that the writing of a memory cell in which data has not been sufficiently written is again performed in accordance with the contents of the data circuit and a state after data has been written in the memory cell.
According to a fifteenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level (n is a natural number not smaller than 3) which can electrically be rewritten are arranged in a matrix manner;
threshold detection means for detecting the threshold voltage of the memory cell;
a data circuit for storing data to be written in the memory cell; and
verify means for verifying whether or not the state after data has been written in the memory cell has been a required data storing state,
wherein detection of the threshold voltage is performed such that first threshold detection voltage is applied to a gate electrode of the memory cell to determine whether the memory cell is (i) in a xe2x80x9c1xe2x80x9d state or (ii) in a xe2x80x9c2 or morexe2x80x9d state (i.e., xe2x80x9c2xe2x80x9d, xe2x80x9c3xe2x80x9d, . . . , or xe2x80x9cnxe2x80x9d state), second threshold detection voltage is applied to the gate electrode of the memory cell to determine whether the memory cell is (i) in xe2x80x9c1 or 2xe2x80x9d state (i.e., xe2x80x9c1xe2x80x9d or xe2x80x9c2xe2x80x9d state) or (ii) xe2x80x9c3 or morexe2x80x9d state (i.e., xe2x80x9c3xe2x80x9d, xe2x80x9c4xe2x80x9d, . . . , or xe2x80x9cn statexe2x80x9d), third to (nxe2x88x921)-th threshold detection voltage is applied to the gate electrode of the memory cell, and reference to the potential of a signal line from which data to be written in the memory cell has been output is made two or more times to update the contents of the data circuit in such a manner that the writing of a memory cell in which data has not been sufficiently written is again performed in accordance with the contents of the data circuit and a state of the memory cell after data has been written.
According to a sixteenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing n-level (n is a natural number not smaller than 3) and being able to be electrically rewritten are arranged in a matrix manner;
m data circuits for storing data to be written in the memory cell;
verify means for verifying whether or not the state of the memory cell after data has been written has been a required data storing state; and
means for simultaneously updating contents of the data circuit, which is formed of a data updating circuit for simultaneously updating the contents of the data circuit to again write data in only a memory cell in which data has not been sufficiently written in accordance with the contents of the data circuit and the state of the memory cell after data has been written, wherein the data update circuit makes a reference to the contents of one data circuit.
According to a seventeenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
means for charging the bit line with one of bit line write potentials corresponding to multilevel data when multilevel data is written in the memory cell and brining the bit line to an electrically floating state; and
means for causing the potential of the bit line to have a bit line write control potential determined in accordance with multilevel data by increasing, decreasing or maintaining the quantity of charge of the bit line.
According to an eighteenth aspect of the present invention, there is provided a nonvolatile-semiconductor memory device comprising:
a memory cell array in which memory cells for storing binary or higher level data are arranged in a matrix manner;
a bit line used for writing data in the memory cell and reading data from the memory cell; and
a bit line controller for making the bit line to a predetermined potential and then bringing the bit line to an electrically floating state,
wherein the bit line is set to a predetermined potential and then is brought to an electrically floating state, and when data is written in the memory cell, the predetermined potential of the bit line is used as one of bit line write control voltages.
According to a nineteenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cells for storing binary or higher level data are arranged in a matrix manner;
a bit line for transferring data to be written in the memory cell and data read from the memory cell;
a first circuit connected to the bit line to make the potential of the bit line to a predetermined level before data is written in the memory cell and bring the bit line to an electrically floating state; and
a second circuit connected to the bit line for maintaining the potential of the bit line at the predetermined level when one of binary or higher level data is written in a selected memory cell and shifting the potential of the bit line to a level different from the predetermined level when another binary or higher level data is written in a selected memory cell.
According to the nonvolatile semiconductor memory device of the nineteenth aspect, the second circuit includes a flip-flop circuit, and the flip-flop circuit stores data to be written when data is written in the memory cell.
According to the nonvolatile semiconductor memory device of the nineteenth aspect, the flip-flop circuit maintains the potential of the bit line at the predetermined level or shifts the potential to a level different from the predetermined level in accordance with stored data to be written when data is written in the memory cell.
According to the nonvolatile semiconductor memory device of the nineteenth aspect, the flip-flop circuit amplifies and stores read data when data is read from the memory cell.
According to the nonvolatile semiconductor memory device of the nineteenth aspect, the number of data to be stored by the memory cell is n (nxe2x89xa72), the number of the flip-flop circuits for storing data to be written in the memory cell and amplifies and stores data read from the memory cell is (nxe2x88x921).
According to the nonvolatile semiconductor memory device of the nineteenth aspect, write data stored by (nxe2x88x921) flip-flop circuits is changed to another data after a verify operation has been completed.
According to the nonvolatile semiconductor memory device of the nineteenth aspect, there is further provided a write completion detecting circuit for detecting change of write data stored by (nxe2x88x921) flip-flop circuits into another data to complete a writing operation when the write completion detecting circuit has detected the change.
According to a twentieth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising:
a memory cell array in which memory cell for storing binary or higher level data are arranged in a matrix manner;
a bit line connected to a source and a drain of the memory cell; and
a bit line controller connected between the bit line and a data input/output line,
wherein the bit line controller has a charging circuit for charging the bit line before a writing operation, a write data storing portion for storing write data supplied to the data input/output line, and a data controller for maintaining the potential of the bit line at the charged level or shifting the potential from the charged level in accordance with write data stored by the write data storing portion.
According to the nonvolatile semiconductor memory device of the twenties aspect, the data controller includes a flip-flop circuit, and the flip-flop circuit stores write data supplied to the data input/output line when data is written in the memory cell.
According to the nonvolatile semiconductor memory device of the twenties aspect, the flip-flop circuit amplifies data read to the bit line to supply read data to the data input/output line.
According to the nonvolatile semiconductor memory device of the twenties aspect, when the number of data to be stored by the memory cell is n (nxe2x89xa72), the number of the flip-flop circuits for storing data to be written in the memory cell and amplifies and stores data read from the memory cell is (nxe2x88x921).
According to the nonvolatile semiconductor memory device of the twenties aspect, write data to be stored by (nxe2x88x921) flip-flop circuits is changed to another data after a verification operation has been completed.
According to the nonvolatile semiconductor memory device of the twenties aspect, there is further provided a write completion detecting circuit for detecting change of write data stored by (nxe2x88x921) flip-flop circuits into another data to complete a writing operation when the write completion detecting circuit has detected the change.
According to the nonvolatile semiconductor memory device of the twenties aspect, the charging circuit charges the bit line to a power supply potential.
According to the nonvolatile semiconductor memory device of the twenties aspect, the data controller maintains the potential of the bit line at the power supply potential or makes the potential to be lower than the power supply potential.
According to the nonvolatile semiconductor memory device of the twenties aspect, the charging circuit charges the bit line to a potential between a ground voltage and the power supply voltage.
According to the nonvolatile semiconductor memory device of the twenties aspect, the data controller maintains the potential of the bit line at the intermediate potential, makes the potential to be lower than the intermediate potential or makes the potential to be higher than the intermediate potential in accordance with write data stored by the write data storing portion included in the data controller.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention.
The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.